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INTEGRATED CIRCUITS
74F191 Up/down binary counter with reset and ripple clock
Product specification IC15 Data Handbook 1995 Jul 17
Philips Semiconductors
Philips Semiconductors
Product specification
Up/Down binary counter with reset and ripple clock
74F191
FEATURES
* High speed -125MHz typical fMAX * Synchronous, reversible counting * 4-Bit binary * Asynchronous parallel load capability * Cascadable without external logic * Single up/down control input
DESCRIPTION
The 74F191 is a 4-bit binary counter. It contains four edge-triggered master/slave flip-flops with internal gating and steering logic to provide asynchronous preset and synchronous count-up and count-down operations. Asynchronous parallel load capability permits the counter to be preset to any desired number. Information present on the parallel data inputs (D0 - D3) is loaded into the counter and appears on the outputs when the Parallel Load (PL) input is Low. This operation overrides the counting function. Counting is inhibited by a High level on the count enable (CE) input. When CE is Low, internal state changes are initiated. Overflow/underflow indications are provided by two types of outputs, the Terminal Count (TC) and Ripple Clock (RC). The TC output is normally Low and goes High when: 1) the count reaches zero in the countdown mode or 2) reaches "15" in the count up mode. The TC output will remain High until a state change occurs, either by counting or presetting, or until U/D is changed. TC output should not be used as a clock signal because it is subject to decoding spikes. The TC signal is used internally to enable the RC output. When TC is High and CE is Low, the RC follows the clock pulse. The RC output essentially duplicates the Low clock pulse width, although delayed in time by two gate delays.
PIN CONFIGURATION
D1 1 Q1 Q0 2 3 16 VCC 15 D0 14 CP 13 RC 12 TC 11 PL 10 D2 9 D3
CE 4 U/D 5 Q2 Q3 6 7
GND 8
SF00729
TYPE 74F191
TYPICAL fMAX 125MHz
TYPICAL SUPPLY CURRENT (TOTAL) 40mA
ORDERING INFORMATION
DESCRIPTION 16-pin plastic DIP 16-pin plastic SO COMMERCIAL RANGE VCC = 5V 10%, Tamb = 0C to +70C N74F191N N74F191D PKG DWG # SOT38-4 SOT109-1
INPUT AND OUTPUT LOADING AND FAN-OUT TABLE
PINS D0 - D3 CE CP PL U/D Q 0 - Q3 RC TC Data inputs Count enable input (active Low) Clock pulse input (active rising edge) Asynchronous parallel load control input (active Low) Up/down count control input Flip-flop outputs Ripple clock output (active low) Terminal count output DESCRIPTION 74F(U.L.) HIGH/LOW 1.0/1.0 1.0/3.0 1.0/1.0 1.0/1.0 1.0/1.0 50/33 50/33 50/33 LOAD VALUE HIGH/LOW 20A/0.6mA 20A/1.8mA 20A/0.6mA 20A/0.6mA 20A/0.6mA 1.0mA/20mA 1.0mA/20mA 1.0mA/20mA
NOTE: One (1.0) FAST Unit Load (U.L.) is defined as: 20A in the High state and 0.6mA in the Low state.
1995 Jul 17
2
853-0352 15459
Philips Semiconductors
Product specification
Up/Down binary counter with reset and ripple clock
74F191
LOGIC SYMBOL
15 1 10 9
LOGIC SYMBOL (IEEE/IEC)
4 5 EN1 CTR DIV 10 2(CT=0)Z6 3(CT=15)Z6 6, 4, 1 12
M2[DOWN] M3[UP]
4 5 14 11
D0 CE U/D CP PL Q0 3
D1
D2
D3 14 RC TC 13
1,2-/1,3+ G4
13
11 12 15 1 Q1 2 Q2 6 Q3 7 10 9
C5 [LOAD] 5D [1] [2] [4] [8] +- 3 2 6 7
VCC=Pin 16 GND=Pin 8
SF00730
SF00731
LOGIC DIAGRAM
D0 PL 11 15 D1 1 D2 10 D3 9
U/D
5
4 CE 14 CP J SD Q CP K RD Q J SD Q CP K RD Q J SD Q CP K RD Q J SD Q CP K RD Q
13 VCC = Pin 16 GND = Pin 8
12 Q0
3 Q1
2 Q2
6 Q3
7
RC TC
SF00732
1995 Jul 17
3
Philips Semiconductors
Product specification
Up/Down binary counter with reset and ripple clock
74F191
MODE SELECT -- FUNCTION TABLE
INPUTS PL L L H H H U/D X X L H X CE X X l l H CP X X X Dn L H X X X OUTPUTS Qn L H Count up Count down No change Parallel load Count up Count down Hold (do nothing) OPERATING MODE
TC AND RC FUNCTION TABLE
INPUTS U/D H L L L H H CE H H L H H L X X CP X X Q0 H H H L L L TERMINAL COUNT STATE Q1 H H H L L L Q2 H H H L L L Q3 H H H L L L TC L H H L H H H H OUTPUTS RC H H
H = High voltage level steady state L = Low voltage level steady state X = Don't care = Low pulse = Low-to-High clock transition l = Low voltage level one set-up time prior to the Low-to-High clock transition
1995 Jul 17
4
Philips Semiconductors
Product specification
Up/Down binary counter with reset and ripple clock
74F191
APPLICATIONS
DIRECTION CONTROL U/D ENABLE CLOCK CE CP RC U/D CE CP RC U/D CE CP RC
a. N-Stage Counter Using Ripple Clock
DIRECTION CONTROL U/D ENABLE CE CP RC U/D CE CP RC U/D CE CP RC
CLOCK
b. Synchronous N-Stage Counter with Common Clock Using Ripple/Clock
DIRECTION CONTROL ENABLE
U/D CE CP CLOCK * = Carry Gate
U/D
U/D
*
TC
CE CP
*
TC
CE CP
TC
c. Synchronous N-Stage Counter with Common Clock and Terminal Count
SF00733
Figure 1. The 74F191 simplifies the design of multi-stage counters, as indicated in Figure 1, each RC output is used as the clock input for the next higher stage. When the clock source has a limited drive capability this configuration is particularly advantageous, since the clock source drives only the first stage. It is only necessary to inhibit the first stage to prevent counting in all stages, since a High signal on CE inhibits the RC output pulse as indicated in the Mode Select Table. The timing skew between state changes in the first and last stages is represented by the cumulative delay of the clock as it ripples through the preceding stages. This is a disadvantage of the configuration in some applications. Figure 1b shows a method of causing state changes to occur simultaneously in all stages. The RC output signals propagate in ripple fashion and all clock inputs are driven in parallel. The Low state duration of the clock in this configuration must be long enough to allow the negative-going edge of the RC signal to ripple through to the last stage before the clock goes High. Since the RC output of any package goes High shortly after its clock input goes High, there is no such restriction on the High state duration of the clock. In Figure 1c, the configuration shown avoids ripple delays and their associated restrictions. The combined TC signals from all the preceding stages forms the CE input signal for a given stage. An enable signal must also be included in each carry gate in order to inhibit counting. The TC output of a given stage is not affected by its own CE, therefore, the simple inhibit scheme of Figure 1a and 1b does not apply.
1995 Jul 17
5
Philips Semiconductors
Product specification
Up/Down binary counter with reset and ripple clock
74F191
ABSOLUTE MAXIMUM RATINGS
(Operation beyond the limits set forth in this table may impair the useful life of the device. Unless otherwise noted these limits are over the operating free-air temperature range.) SYMBOL VCC VIN IIN VOUT IOUT Tamb Tstg Supply voltage Input voltage Input current Voltage applied to output in High output state Current applied to output in Low output state Operating free-air temperature range Storage temperature PARAMETER RATING -0.5 to +7.0 -0.5 to +7.0 -30 to +5.0 -0.5 to +VCC 40 0 to +70 -65 to +150 UNIT V V mA V mA
oC oC
RECOMMENDED OPERATING CONDITIONS
SYMBOL VCC VIH VIL IIK IOH IOL Tamb Supply voltage High-level input voltage Low-level input voltage Input clamp current High-level output current Low-level output current Operating free-air temperature range 0 PARAMETER LIMITS Min 4.5 2.0 0.8 -18 -1 20 70 Nom 5.0 Max 5.5 UNIT V V V mA mA mA
oC
DC ELECTRICAL CHARACTERISTICS
(Over recommended operating free-air temperature range unless otherwise noted.) SYMBOL PARAMETER TEST CONDITIONS1 VCC = Min, VIL = Max, IOH = Max, VIH = Min VCC = Min, VIL = Max, IOL = Max, VIH = Min VCC = Min, II = IIK VCC = Max, VI = 7.0V VCC = Max, VI = 2.7V CE Others IOS Short-circuit output current3 current4 VCC = Max VI = 0 5V Max, 0.5V VCC = Max -60 10%VCC 5%VCC 10%VCC 5%VCC LIMITS Min 2.5 2.7 3.4 0.30 0.30 -0.73 0.50 0.50 -1.2 100 20 -1.8 -0.6 -150 Typ2 Max UNIT V V V V V A A mA mA mA
VO OH
High-level High level output voltage
VO OL VIK II IIH IIL
Low-level Low level output voltage Input clamp voltage Input current at maximum input voltage High-level input current Low-level input current
ICC Supply (total) VCC = Max 40 55 mA NOTES: 1. For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions for the applicable type. 2. All typical values are at VCC = 5V, Tamb = 25C. 3. Not more than one output should be shorted at a time. For testing IOS, the use of high-speed test apparatus and/or sample-and-hold techniques are preferable in order to minimize internal heating and more accurately reflect operational values. Otherwise, prolonged shorting of a High output may raise the chip temperature well above normal and thereby cause invalid readings in other parameter tests. In any sequence of parameter tests, IOS tests should be performed last. 4. Measure ICC all inputs grounded and all outputs open.
1995 Jul 17
6
Philips Semiconductors
Product specification
Up/Down binary counter with reset and ripple clock
74F191
AC ELECTRICAL CHARACTERISTICS
LIMITS SYMBOL PARAMETER TEST CONDITIONS Tamb= +25C VCC = +5.0V CL = 50pF, RL = 500 Min fMAX fMAX tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL Maximum clock frequency to Qn outputs Maximum clock frequency to RC outputs Propagation delay CP to Qn Propagation delay CP to TC Propagation delay CP to RC Propagation delay CE to RC Propagation delay U/D to RC Propagation delay U/D to TC Propagation delay Dn to Qn Propagation delay Dn to TC Propagation delay Dn to RC Propagation delay PL to Qn Propagation delay PL to TC Propagation delay PL to RC Waveform 1 Waveform 1 Waveform 1 Waveform 1 Waveform 2 Waveform 2 Waveform 2 Waveform 4 Waveform 3 Waveform 3 Waveform 4 Waveform 3 Waveform 4 Waveform 5 Waveform 5 Waveform 5 100 85 2.5 5.0 6.5 6.0 2.5 3.0 2.0 3.0 8.0 4.5 4.0 3.0 2.0 6.5 5.5 6.5 6.0 6.0 4.5 5.5 5.5 6.0 8.5 7.5 Typ 125 95 4.5 7.5 9.0 8.0 4.5 5.0 4.0 5.0 11.0 7.5 6.5 6.0 4.0 9.0 9.5 9.5 14.0 11.0 6.5 8.0 8.5 10.5 16.0 10.0 8.0 11.5 12.5 11.0 7.5 7.5 7.0 7.5 16.0 10.5 9.5 9.5 7.0 12.0 13.0 13.0 18.0 13.5 9.5 11.5 12.0 13.5 18.5 13.0 Max Tamb= 0C to +70C VCC = +5.0V 10% CL = 50pF, RL = 500 Min 90 75 2.0 5.0 6.0 6.0 2.0 2.5 2.0 3.0 8.0 4.0 3.0 3.0 1.5 6.5 5.0 6.0 6.0 6.0 4.0 5.0 5.5 6.0 8.5 7.0 8.5 12.0 13.0 12.0 8.0 8.0 7.5 8.0 17.0 11.0 10.5 10.0 7.5 13.0 14.0 14.0 19.5 15.0 10.5 12.0 13.0 14.5 21.0 13.5 Max MHz MHz ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns UNIT
1995 Jul 17
7
Philips Semiconductors
Product specification
Up/Down binary counter with reset and ripple clock
74F191
AC SETUP REQUIREMENTS
LIMITS SYMBOL PARAMETER TEST CONDITIONS Tamb= +25C VCC = +5.0V CL = 50pF, RL = 500 Min ts(H) ts(L) th(H) th(L) ts(L) th(L) ts(H) ts(L) th(H) th(L) tw(H) tw(L) tw(L) trec Setup time, High or Low Dn to PL Hold time, High or Low Dn to PL Setup time, Low CE to CP Hold time, Low CE to CP Setup time, High or Low U/D to CP Hold time, High or Low U/D to CP CP Pulse width, High or Low PL Pulse width, Low Recovery time, PL to CP Waveform 6 Waveform 6 Waveform 6 Waveform 6 Waveform 6 Waveform 6 Waveform 1 Waveform 5 Waveform 5 4.5 4.5 2.0 2.0 10.0 0 12.0 12.0 0 0 3.5 6.0 6.0 6.0 Typ Max Tamb = 0C to +70C VCC = +5.0V 10% CL = 50pF, RL = 500 Min 5.0 5.0 2.0 2.0 10.0 0 12.0 12.0 0 0 3.5 6.0 6.0 6.0 Max ns ns ns ns ns ns ns ns ns ns ns ns ns ns UNIT
1995 Jul 17
8
Philips Semiconductors
Product specification
Up/Down binary counter with reset and ripple clock
74F191
AC WAVEFORMS
NOTE: For all waveforms, VM = 1.5V
1/fMAX CP VM tW(H) tPHL RC, Qn, TC VM tPLH VM tPHL RC VM VM tW(L) CE, CP U/D VM VM VM tPLH
SF00734
SF00735
Waveform 1. Propagation Delay, Clock Input to Output, Clock Pulse Width, and Maximum Clock Frequency.
Waveform 2. Propagation Delay, Clock, Clock Enable or Up/Down to Ripple Clock Output
Dn
VM tPLH
VM tPHL VM VM
U/D, Dn VM tPHL RC, TC VM VM tPLH VM
RC, TC, Qn
SF00736
SF00737
Waveform 3. Propagation Delay, Non-Inverting Path
Waveform 4. Propagation Delay, Inverting Path
PL
VM tW(L)
VM tREC VM
CE, Dn U/D tS(H)
VM tS(L)
th(H) VM
th(L) VM
CP
PL tPLH TC, Qn VM CP
VM
VM
tPHL RC, Qn VM
The shaded areas indicate when the input is permitted to change for predictable output performance.
SF00739 SF00738
Waveform 6. Data Set Up and Hold Times
Waveform 5. Parallel Load Pulse Width, Parallel Load to Output Delay and Parallel Load to Clock Recovery Time
1995 Jul 17
9
Philips Semiconductors
Product specification
Up/Down binary counter with reset and ripple clock
74F191
TEST CIRCUIT AND WAVEFORM
VCC NEGATIVE PULSE VIN PULSE GENERATOR RT D.U.T. VOUT 90% VM 10% tTHL (tf ) CL RL tw VM 10% tTLH (tr ) 0V 90% AMP (V)
tTLH (tr ) 90% POSITIVE PULSE VM 10% tw
tTHL (tf ) AMP (V) 90% VM 10% 0V
Test Circuit for Totem-Pole Outputs DEFINITIONS: RL = Load resistor; see AC ELECTRICAL CHARACTERISTICS for value. CL = Load capacitance includes jig and probe capacitance; see AC ELECTRICAL CHARACTERISTICS for value. RT = Termination resistance should be equal to ZOUT of pulse generators.
Input Pulse Definition INPUT PULSE REQUIREMENTS family amplitude VM 74F 3.0V 1.5V rep. rate 1MHz tw 500ns tTLH 2.5ns tTHL 2.5ns
SF00006
1995 Jul 17
10
Philips Semiconductors
Product specification
Up/down binary counter with reset and ripple clock
74F191
DIP16: plastic dual in-line package; 16 leads (300 mil)
SOT38-4
1995 Jul 17
11
Philips Semiconductors
Product specification
Up/down binary counter with reset and ripple clock
74F191
SO16: plastic small outline package; 16 leads; body width 3.9 mm
SOT109-1
1995 Jul 17
12
Philips Semiconductors
Product specification
Up/down binary counter with reset and ripple clock
74F191
NOTES
1995 Jul 17
13
Philips Semiconductors
Product specification
Up/down binary counter with reset and ripple clock
74F191
Data sheet status
Data sheet status Objective specification Preliminary specification Product specification Product status Development Qualification Definition [1] This data sheet contains the design target or goal specifications for product development. Specification may change in any manner without notice. This data sheet contains preliminary data, and supplementary data will be published at a later date. Philips Semiconductors reserves the right to make chages at any time without notice in order to improve design and supply the best possible product. This data sheet contains final specifications. Philips Semiconductors reserves the right to make changes at any time without notice in order to improve design and supply the best possible product.
Production
[1] Please consult the most recently issued datasheet before initiating or completing a design.
Definitions
Short-form specification -- The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see the relevant data sheet or data handbook. Limiting values definition -- Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information -- Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification.
Disclaimers
Life support -- These products are not designed for use in life support appliances, devices or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application. Right to make changes -- Philips Semiconductors reserves the right to make changes, without notice, in the products, including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified. Philips Semiconductors 811 East Arques Avenue P.O. Box 3409 Sunnyvale, California 94088-3409 Telephone 800-234-7381 (c) Copyright Philips Electronics North America Corporation 1998 All rights reserved. Printed in U.S.A. print code Document order number: Date of release: 10-98 9397-750-05093
Philips Semiconductors
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